The invention relates generally to the field of conserving power in integrated circuit devices. More particularly, the invention relates to power reduction design and circuitry in a digital signal processing integrated circuit.
Power consumption in an integrated circuit can be caused by many factors, including the power required to switch parasitic capacitance in the wiring of an integrated circuit. The equation for computing average power dissipated in a capacitor each time that it is switched is   P  =            1      2        ⁢          CV      2        ⁢          F      .      
There are a number of well known ways to reduce power consumption in an integrated circuit. One well known way is to reduce the power supply voltage that is provided to the integrated circuit. Another well known way is to reduce the frequency F at which circuitry and any capacitance is switched. Usually this is done by shutting off clocks to certain clocked circuitry in unnecessary functional blocks.
As integrated circuits have become functionally more complex, it has become ever more important to reduce power consumption. This is particularly important in integrated circuits with many transistors, wide data buses and large memory arrays. Access to a memory array that stores operands may be very frequent, particularly in digital signal processing applications so it is important to reduce power consumption in these instances.
Power reduction is important in order to reduce the heating of the integrated circuit to avoid damage and lower packaging costs for the integrated circuit.